Features
Table 1–1
shows the MAX II family features.
Table 1–1. MAX II Family Features
Feature
LEs
Typical Equivalent
Macrocells
Equivalent Macrocell
Range
UFM Size (bits)
Maximum User I/O pins
t
PD1
(ns)
(1)
f
CNT
(MHz)
(2)
t
SU
(ns)
t
CO
(ns)
Notes to
Table 1–1:
(1)
(2)
t
PD1
represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and
combinational logic implemented in a single LUT and LAB that is adjacent to the output pin.
The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay
will run faster than this number.
EPM240
EPM570
EPM240G EPM570G
240
192
570
440
EPM1270
EPM1270G
1,270
980
EPM2210
EPM2210G
2,210
1,700
EPM240Z
240
192
128 to 240
8,192
80
7.5
152
2.3
6.5
EPM570Z
570
440
240 to 570
8,192
160
9.0
152
2.2
6.7
128 to 240 240 to 570 570 to 1,270 1,270 to 2,210
8,192
80
4.7
304
1.7
4.3
8,192
160
5.4
304
1.2
4.5
8,192
212
6.2
304
1.2
4.6
8,192
272
7.0
304
1.2
4.6
f
MAX II
Logic Element to Macrocell Conversion Methodology
white paper.
MAX II and MAX IIG devices are available in three speed grades: –3, –4,
and –5, with –3 being the fastest. Similarly, MAX IIZ devices are available
in two speed grades: –6, –7, with –6 being faster. These speed grades
represent the overall relative performance, not any specific timing
parameter. For propagation delay timing numbers within each speed
grade and density, refer to the
DC and Switching Characteristics
chapter in
the
MAX II Device Handbook.
1–2
MAX II Device Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
December 2007
ALTERA [ ALTERA CORPORATION ]
