Global Signals
The UFM block communicates with the logic array similar to LAB-to-LAB
interfaces. The UFM block connects to row and column interconnects and
has local interconnect regions driven by row and column interconnects.
This block also has DirectLink interconnects for fast connections to and
from a neighboring LAB. For more information about the UFM interface
to the logic array, see “User Flash Memory Block” on page 2–23.
Table 2–2 shows the MAX II device routing scheme.
Table 2–2. MAX II Device Routing Scheme
Destination
R4 (1) C4 (1) LE
Source
LUT Register Local DirectLink
UFM Column Row FastI/O
Chain Chain
(1)
(1)
Block
IOE
IOE
(1)
LUT Chain
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
v
Register
Chain
—
—
—
—
—
—
Local
Interconnect
—
—
—
—
—
—
—
—
—
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
v
—
—
—
v
—
—
—
v
—
—
—
DirectLink
Interconnect
R4
v
v
v
v
Interconnect
C4
Interconnect
LE
—
—
—
—
—
—
—
—
v
—
—
—
v
—
—
—
v
v
—
v
v
—
v
v
—
v
v
v
v
v
—
—
—
v
—
—
—
v
—
—
—
UFM Block
Column IOE
Row IOE
—
v
v
Note to Table 2–2:
(1) These categories are interconnects.
Each MAX II device has four dual-purpose dedicated clock pins
Global Signals
(GCLK[3..0], two pins on the left side and two pins on the right side)
that drive the global clock network for clocking, as shown in Figure 2–13.
These four pins can also be used as general-purpose I/O if they are not
used to drive the global clock network.
The four global clock lines in the global clock network drive throughout
the entire device. The global clock network can provide clocks for all
resources within the device including LEs, LAB local interconnect, IOEs,
and the UFM block. The global clock lines can also be used for global
2–20Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
March 2008
ALTERA [ ALTERA CORPORATION ]
