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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Logic Elements  
LE Operating Modes  
The MAX II LE can operate in one of the following modes:  
“Normal Mode”  
“Dynamic Arithmetic Mode”  
Each mode uses LE resources differently. In each mode, eight available  
inputs to the LE, the four data inputs from the LAB local interconnect,  
carry-in0and carry-in1from the previous LE, the LAB carry-in  
from the previous carry-chain LAB, and the register chain connection are  
directed to different destinations to implement the desired logic function.  
LAB-wide signals provide clock, asynchronous clear, asynchronous  
preset/load, synchronous clear, synchronous load, and clock enable  
control for the register. These LAB-wide signals are available in all LE  
modes. The addnsubcontrol signal is allowed in arithmetic mode.  
The Quartus II software, in conjunction with parameterized functions  
such as library of parameterized modules (LPM) functions, automatically  
chooses the appropriate mode for common functions such as counters,  
adders, subtractors, and arithmetic functions.  
Normal Mode  
The normal mode is suitable for general logic applications and  
combinational functions. In normal mode, four data inputs from the LAB  
local interconnect are inputs to a four-input LUT (see Figure 2–7). The  
Quartus II Compiler automatically selects the carry-in or the data3  
signal as one of the inputs to the LUT. Each LE can use LUT chain  
connections to drive its combinational output directly to the next LE in  
the LAB. Asynchronous load data for the register comes from the data3  
input of the LE. LEs in normal mode support packed registers.  
2–10Core Version a.b.c variable  
MAX II Device Handbook, Volume 1  
Altera Corporation  
March 2008  
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