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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX II Architecture  
Each LAB can use two clocks and two clock enable signals. Each LAB’s  
clock and clock enable signals are linked. For example, any LE in a  
particular LAB using the labclk1signal also uses labclkena1. If the  
LAB uses both the rising and falling edges of a clock, it also uses both  
LAB-wide clock signals. Deasserting the clock enable signal turns off the  
LAB-wide clock.  
Each LAB can use two asynchronous clear signals and an asynchronous  
load /preset signal. By default, the Quartus II software uses a NOT gate  
push-back technique to achieve preset. If you disable the NOT gate  
push-back option or assign a given register to power-up high using the  
Quartus II software, the preset is then achieved using the asynchronous  
load signal with asynchronous load data input tied high.  
With the LAB-wide addnsubcontrol signal, a single LE can implement a  
one-bit adder and subtractor. This saves LE resources and improves  
performance for logic functions such as correlators and signed  
multipliers that alternate between addition and subtraction depending  
on data.  
The LAB column clocks [3..0], driven by the global clock network, and  
LAB local interconnect generate the LAB-wide control signals. The  
MultiTrack interconnect structure drives the LAB local interconnect for  
non-global control signal generation. The MultiTrack interconnect’s  
inherent low skew allows clock and control signal distribution in addition  
to data. Figure 2–5 shows the LAB control signal generation circuit.  
Figure 2–5. LAB-Wide Control Signals  
Dedicated  
LAB Column  
Clocks  
4
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
labclkena2  
labclkena1  
syncload  
labclr2  
addnsub  
Local  
Interconnect  
labclk1  
labclk2  
asyncload  
or labpre  
labclr1  
synclr  
Altera Corporation  
March 2008  
2–7  
MAX II Device Handbook, Volume 1