FLEX 6000 Programmable Logic Device Family Data Sheet
shows FLEX 6000 performance for more complex designs.
Table 4. FLEX 6000 Device Performance for Complex Designs
Application
LEs Used
-1 Speed
Grade
8-bit, 16-tap parallel finite impulse response
(FIR) filter
8-bit, 512-point fast Fourier transform (FFT)
function
a16450
universal asynchronous
receiver/transmitter (UART)
PCI bus target with zero wait states
Note:
(1)
Performance
-2 Speed
Grade
80
89
53
30
49
Units
-3 Speed
Grade
72
109
43
25
42
MSPS
µS
MHz
MHz
MHz
599
1,182
487
609
94
75
63
36
56
The applications in this table were created using Altera MegaCore
TM
functions
.
FLEX 6000 devices are supported by Altera development systems; a
single, integrated package that offers schematic, text (including AHDL),
and waveform design entry, compilation and logic synthesis, full
simulation and worst-case timing analysis, and device configuration. The
Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL,
and other interfaces for additional design entry and simulation support
from other industry-standard PC- and UNIX workstation-based EDA
tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development systems include DesignWare
functions that are optimized for the FLEX 6000 architecture.
The Altera development system runs on Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800.
f
See the
and the
for more information.
4
Altera Corporation
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