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EPF6024AQC240-3N 参数 Datasheet PDF下载

EPF6024AQC240-3N图片预览
型号: EPF6024AQC240-3N
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 52 页 / 405 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 6000 Programmable Logic Device Family Data Sheet  
Carry Chain  
The carry chain provides a very fast (0.1 ns) carry-forward function  
between LEs. The carry-in signal from a lower-order bit drives forward  
into the higher-order bit via the carry chain, and feeds into both the LUT  
and the next portion of the carry chain. This feature allows the FLEX 6000  
architecture to implement high-speed counters, adders, and comparators  
of arbitrary width. Carry chain logic can be created automatically by the  
Altera software during design processing, or manually by the designer  
during design entry. Parameterized functions such as LPM and  
DesignWare functions automatically take advantage of carry chains for  
the appropriate functions.  
Because the first LE of each LAB can generate control signals for that LAB,  
the first LE in each LAB is not included in carry chains. In addition, the  
inputs of the first LE in each LAB may be used to generate synchronous  
clear and load enable signals for counters implemented with carry chains.  
Carry chains longer than nine LEs are implemented automatically by  
linking LABs together. For enhanced fitting, a long carry chain skips  
alternate LABs in a row. A carry chain longer than one LAB skips either  
from an even-numbered LAB to another even-numbered LAB, or from an  
odd-numbered LAB to another odd-numbered LAB. For example, the last  
LE of the first LAB in a row carries to the second LE of the third LAB in  
the row. In addition, the carry chain does not cross the middle of the row.  
For instance, in the EPF6016 device, the carry chain stops at the 11th LAB  
in a row and a new carry chain begins at the 12th LAB.  
Figure 5 shows how an n-bit full adder can be implemented in n + 1 LEs  
with the carry chain. One portion of the LUT generates the sum of two bits  
using the input signals and the carry-in signal; the sum is routed to the  
output of the LE. Although the register can be bypassed for simple adders,  
it can be used for an accumulator function. Another portion of the LUT  
and the carry chain logic generates the carry-out signal, which is routed  
directly to the carry-in signal of the next-higher-order bit. The final  
carry-out signal is routed to an LE, where it is driven onto the FastTrack  
Interconnect.  
10  
Altera Corporation