Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Timing Information
3–27
Timing Information
shows the timing waveform for write operation to the serial configuration
device.
Figure 3–18.
Write Operation Timing
t
CSH
nCS
t
NCSH
DCLK
t
DSU
ASDI
Bit
n
t
DH
Bit
n
1
Bit 0
t
NCSSU
t
CH
t
CL
DATA
High Impedance
defines the serial configuration device timing parameters for write
operation.
Table 3–16.
Write Operation Parameters
Symbol
f
WCLK
Parameter
Write clock frequency (from FPGA, download cable, or
embedded processor) for write enable, write disable,
read status, read silicon ID, write bytes, erase bulk, and
erase sector operations
DCLK
high time
DCLK
low time
Chip select (nCS) setup time
Chip select (nCS) hold time
Data (ASDI) in setup time before rising edge on
DCLK
Data (ASDI) hold time after rising edge on
DCLK
Chip select high time
Write bytes cycle time for EPCS1, EPCS4, EPCS16, and
EPCS64
Write bytes cycle time for EPCS128
t
WS
t
EB
Write status cycle time
Erase bulk cycle time for EPCS1
Erase bulk cycle time for EPCS4
Erase bulk cycle time for EPCS16
Erase bulk cycle time for EPCS64
Erase bulk cycle time for EPCS128
t
ES
Erase sector cycle time for EPCS1, EPCS4, EPCS16,
and EPCS64
Erase sector cycle time for EPCS128
Note to
(1) These parameters are not shown in
Min
—
Typ
—
Max
25
Unit
MHz
t
CH
t
CL
t
NCSSU
t
NCSH
t
DSU
t
DH
t
CSH
t
WB
20
20
10
10
5
5
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
2.5
5
3
5
17
68
105
2
2
—
—
—
—
—
—
—
5
7
15
6
10
40
160
250
3
6
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
s
s
s
s
s
s
s
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