Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Serial Configuration Device Memory Access
3–15
Table 3–8.
Operation Codes for Serial Configuration Devices
Operation
Write enable
Write disable
Read status
Read bytes
Read silicon ID
Fast read
Write status
Write bytes
Erase bulk
Erase sector
Read Device
Identification
Notes to
(1) The MSB is listed first and the least significant bit (LSB) is listed last.
(2) The status register, data or silicon ID are read out at least once on the
DATA
pin and will continuously be read out until
nCS
is driven high.
(3) Write bytes operation requires at least one data byte on the
DATA
pin. If more than 256 bytes are sent to the device, only the last 256 bytes
are written to the memory.
(4) Read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64.
(5) Read Device Identification operation is available only for EPCS128.
Operation Code
0000 0110
0000 0100
0000 0101
0000 0011
1010 1011
0000 1011
0000 0001
0000 0010
1100 0111
1101 1000
1001 1111
Address Bytes
0
0
0
3
0
3
0
3
0
3
0
Dummy Bytes
0
0
0
0
3
1
0
0
0
0
2
Data Bytes
0
0
1 to infinite
1 to infinite
1 to infinite
1 to infinite
1
1 to 256
0
0
1 to infinite
DCLK
f
MAX
(MHz)
25
25
25
20
25
40
25
25
25
25
25
Write Enable Operation
The write enable operation code is
b'0000 0110,
and the MSB is listed first. The
write enable operation sets the write enable latch bit, which is bit
1
in the status
register. Always set the write enable latch bit before write bytes, write status, erase
bulk, and erase sector operations.
shows the timing diagram for the write
enable operation.
and
show the status register bit definitions.
Figure 3–5.
Write Enable Operation Timing Diagram
nCS
0
DCLK
Operation Code
ASDI
1
2
3
4
5
6
7
DATA
High Impedance
ALTERA [ ALTERA CORPORATION ]
