Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Figure 4–3. FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-Party
Programmer)
V
CC
(1)
10 kΩ
V
CC
(1)
V
CC
(1)
10 kΩ
Stratix II or
Cyclone Series FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
(2)
nCONFIG
n
nCEO
N.C.
10 kΩ
nCE
MSEL[n]
(3)
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
ASDO
Notes to
and
(1)
(2)
(3)
V
CC
= 3.3-V.
Serial configuration devices cannot be cascaded.
Connect the FPGA
MSEL[]
input pins to select the AS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
The FPGA acts as the configuration master in the configuration flow and
provides the clock to the serial configuration device. The FPGA enables
the serial configuration device by pulling the
nCS
signal low via the
nCSO
signal (See
and
Subsequently, the FPGA sends the
instructions and addresses to the serial configuration device via the
ASDO
signal. The serial configuration device responds to the instructions by
sending the configuration data to the FPGA’s
DATA0
pin on the falling
edge of
DCLK.
The data is latched into the FPGA on the
DCLK
signal’s
rising edge.
The FPGA controls the
nSTATUS
and
CONF_DONE
pins during
configuration in AS mode. If the
CONF_DONE
signal does not go high at
the end of configuration or if the signal goes high too early, the FPGA will
pulse its
nSTATUS
pin low to start reconfiguration. Upon successful
configuration, the FPGA releases the
CONF_DONE
pin, allowing the
external 10-kΩ resistor to pull this signal high. Initialization begins after
the
CONF_DONE
goes high. After initialization, the FPGA enters user
mode.
f
For more information on configuring Stratix II FPGAs in AS mode or
other configuration modes, see
Configuring Stratix II Devices
in the
Configuration Handbook.
Core Version a.b.c variable
4–7
Configuration Handbook, Volume 2
Altera Corporation
July 2004
ALTERA [ ALTERA CORPORATION ]
