EPC1PC8 参数 Datasheet PDF下载

Functional Description

Page 5

Table 2. Supported Configuration Devices (Part 4 of 4)

Device Family

Device

EP2S15

EP2S30

Stratix II

EP2S60

EP2S90

EP2S130

EP2S180

Notes to

(1) Raw Binary File (.rbf) were used to determine these sizes.

(2) This number is calculated with the Cyclone series compression feature enabled.

(3) EP1S10 ES devices requires four EPC2 devices.

Data Size (Bits)

(1)

EPC1064 or

EPC1064V

—

—

—

—

—

—

EPC1213

—

—

—

—

—

—

EPC1441

—

—

—

—

—

—

EPC1

—

—

—

—

—

—

EPC2

3

7

11

17

24

31

5,000,000

10,100,000

17,100,000

27,500,000

39,600,000

52,400,000

shows the configuration device block diagram.

Figure 1. Configuration Device Block Diagram

FPGA (except FLEX 8000)

Configuration

Using

an

EPC2, EPC1,

or

EPC1441

DCLK

Address

Counter

Oscillator

CLK

ENA

nRESET

Oscillator

Control

nCS

Error

Detection

Circuitry

Address

Decode

Logic

nCASC

(1)

(2)

OE

EPROM

Array

DATA

Shift

Register

DATA

FLEX 8000 Device

Configuration

Using

an

EPC1, EPC1441, EPC1213, EPC1064,

or

EPC1064V

DCLK

CLK

ENA

nRESET

Address

Counter

Address

nCS

OE

EPROM

Array

DATA

Shift

Register

Decode

Logic

nCASC

(1)

DATA

Notes to

(1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading.

(2) The

OE

pin is a bidirectional open-drain pin.

January 2012

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices