CF52002
2016.05.04
Fast Passive Parallel Configuration
9
EPC Device Pin
nINIT_CONF
Altera FPGA Pin
nCONFIG
Description
Open-drain output from the EPC device that is used to start FPGA
reconfiguration using the initiate configuration (
INIT_CONF
) JTAG
instruction. This connection is not needed if the
INIT_CONF
JTAG
instruction is not needed. If
nINIT_CONF
is not connected to
nCONFIG
,
nCONFIG
must be tied to VCC either directly or through a pull-up
resistor.
Open-drain bidirectional configuration status signal, which is driven
low by either the EPC device or FPGA during POR and to signal an
error during configuration. Low pulse on
OE
resets the EPC device
controller.
Configuration done output signal driven by the FPGA.
OE
nSTATUS
nCS
CONF_DONE
Fast Passive Parallel Configuration
Stratix series and APEX II devices can be configured using the EPC device in the FPP configuration mode.
In this mode, the EPC device sends a byte of data on the
DATA[7..0]
pins, which connect to the
DATA[7..0]
input pins of the FPGA, per DCLK cycle. Stratix series and APEX II FPGAs receive byte-wide
configuration data per
DCLK
cycle. The following figure shows the EPC device in FPP configuration mode.
In this figure, the external flash interface is not used and hence most flash pins are left unconnected (with
the few noted exceptions).
Enhanced Configuration (EPC) Devices Datasheet
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
