6
Functional Description
CF52002
2016.05.04
Device Family
Grade
Package
Flash Memory
Leaded
Lead-Fee
Commercial
EPC16
Industrial
Military
Commercial/Industrial
UBGA 884
UBGA 884
UBGA 884
PQFP 100
Intel or Sharp
Intel or Sharp
Intel
Intel or Sharp
Intel or Sharp
Intel
Intel
Intel
Note:
The external flash interface feature is supported in EPC4 and EPC16 devices. For more information
about using this feature in the EPC8 device, contact Altera for support.
EPC devices have a 3.3-V core and I/O interface. The controller chip is a synchronous system that
implements the various interfaces and features. The controller chip features three separate interfaces:
• A configuration interface between the controller and the Altera FPGAs
• A JTAG interface on the controller that enables ISP of the flash memory
• An external flash interface that the controller shares with an external processor or FPGA
implementing a Nios embedded processor—an interface available after ISP and configuration
Figure 1: EPC Device Block Diagram
JTAG/ISP Interface
Enhanced Configuration Device
Flash
Shared Flash
Interface
Controller
FPGA
Shared Flash Interface
The EPC device features multiple configuration schemes. In addition to supporting the traditional passive
serial (PS) configuration scheme for a single device or a serial-device chain, the EPC device features
concurrent configuration and parallel configuration. With the concurrent configuration scheme, up to
eight PS device chains can be configured simultaneously. In the FPP configuration scheme, 8-bits of data
Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
