8
Configuration Signals
CF52002
2016.05.04
Depending on the configuration bus width (n), the circuit shifts uncompressed configuration data to the
valid
DATA[n]
pins. Unused
DATA[]
pins drive low.
In addition to transmitting configuration data to the FPGAs, the configuration circuit is also responsible
for pausing configuration whenever there is insufficient data available for transmission. This occurs when
the flash read bandwidth is lower than the configuration write bandwidth. Configuration is paused by
stopping the
DCLK
to the FPGA, when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing
DCLK
”.
The EPC device flash-memories feature a 90-ns access time (approximately 10 MHz). Hence, the flash
read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10
MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to
high configuration write bandwidths. For example, 100-MHz Stratix FPP configuration requires data at
the rate of 800 Mbps (8-bit
DATA[]
bus at 100MHz). This is much higher than the 160 Mbps the flash
memory can support and is the limiting factor for configuration time. Compression increases the effective
flash-read bandwidth as the same amount of configuration data takes up less space in the flash memory
after compression. Since Stratix configuration data compression ratios are approximately two, the
effective read bandwidth doubles to about 320 Mbps.
Finally, the configuration controller also manages errors during configuration. A
CONF_DONE
error occurs
when the FPGA does not de-assert its
CONF_DONE
signal within 64
DCLK
cycles after the last bit of configu‐
ration data is transmitted. When a
CONF_DONE
error is detected, the controller pulses the OE line low,
which pulls the
nSTATUS
signal low and triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in the configuration
data. This corruption could be a result of noise coupling on the board such as poor signal integrity on the
configuration signals. When this error is signaled by the FPGA (by driving the
nSTATUS
signal low), the
controller stops configuration. If the Auto-Restart Configuration After Error option is enabled in the
FPGA, it releases its
nSTATUS
signal after a reset time-out period and the controller attempts to
reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives the
DCLK
pin low and the
DATA[]
pins high. Additionally, the controller tri-states its internal interface to the flash memory, enables the
weak internal pull-ups on the flash address and control lines, and enables bus-keep circuits on flash data
lines.
The following sections describe the different configuration schemes supported by the EPC device—FPP,
PS, and concurrent configuration schemes.
Configuration Signals
Table 4: Configuration Signals Connections Between EPC device and Altera FPGAs.
EPC Device Pin
DATA[]
Altera FPGA Pin
DATA[]
Description
Configuration data transmitted from the EPC device to the FPGA,
which is latched on the rising edge of
DCLK
.
EPC device generated clock used by the FPGA to latch configuration
data provided on the
DATA[]
pins.
DCLK
DCLK
Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
