CF52002
2016.05.04
FPGA Configuration
7
are clocked into the FPGA during each cycle. These configuration schemes offer significantly reduced
configuration times over traditional schemes.
Furthermore, the EPC device features a dynamic configuration or page mode feature. This feature allows
you to dynamically reconfigure all the FPGAs in your system with new images stored in the configuration
memory. Up to eight different system configurations or pages can be stored in the memory and selected
using the PGM[2..0] pins. Your system can be dynamically reconfigured by selecting one of the eight
pages and initiating a reconfiguration cycle.
This page mode feature combined with the external flash interface allows remote and local updates of
system configuration data. The EPC devices are compatible with the remote system configuration feature
of the Stratix device.
Other user programmable features include:
•
•
•
•
Real-time decompression of configuration data
Programmable configuration clock (DCLK)
Flash ISP
Programmable POR delay (PORSEL)
Related Information
•
Provides more information about EPC devices, refer to the PCN0506: Addition of Intel Flash Memory
As
•
FPGA Configuration
FPGA configuration is managed by the configuration controller chip. This process includes reading
configuration data from the flash memory, decompressing the configuration data, transmitting configura‐
tion data using the appropriate
DATA[]
pins, and handling error conditions.
After POR, the controller determines the user-defined configuration options by reading its option bits
from the flash memory. These options include the configuration scheme, configuration clock speed,
decompression, and configuration page settings. The option bits are stored at flash address location
0x8000
(word address) and occupy 512-bits or 32-words of memory. These options bits are read using the
internal flash interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, the configuration controller chip checks if the FPGA is ready to
accept configuration data by monitoring the
nSTATUS
and
CONF_DONE
signals. When the FPGA is ready
(
nSTATUS
is high and
CONF_DONE
is low), the controller begins data transfer using the
DCLK
and
DATA[]
output pins. The controller selects the configuration page to be transmitted to the FPGA by sampling its
PGM[2..0]
pins after POR or reset.
The function of the configuration unit is to transmit decompressed data to the FPGA, depending on the
configuration scheme. The EPC device supports four concurrent configuration modes, with n = 1, 2, 4, or
8 (where n is the number of bits that are sent per
DCLK
cycle on the DATA[n] signals). The value n = 1
corresponds to the traditional PS configuration scheme. The values n = 2, 4, and 8 correspond to
concurrent configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally, the
FPGA can be configured in FPP mode, where eight bits of
DATA
are clocked into the FPGA per
DCLK
cycle.
Enhanced Configuration (EPC) Devices Datasheet
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
