EP4CE15F23C6N 参数 Datasheet PDF下载

型号：	EP4CE15F23C6N
PDF下载：	下载PDF文件查看货源
内容描述：	本节列出了I / O的漏电流，引脚电容，片上端接（ OCT）耐受性，以及Cyclone IV器件总线保持规范。 [This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT) tolerance, and bus hold specifications for Cyclone IV devices.]
分类和应用：	现场可编程门阵列可编程逻辑栅LTE时钟
文件页数/大小：	42 页 / 678 K
品牌：	ALTERA [ ALTERA CORPORATION ]

Chapter 1: Cyclone IV Device Datasheet

1–35

Switching Characteristics

Table 1–42 and Table 1–43 list the IOE programmable delay for Cyclone IV E 1.2 V

core voltage devices.

Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices ^{(1), (2)}

Max Offset

Number

Paths

Affected

Min

Offset

Parameter

Fast Corner

Slow Corner

Unit

Setting

Pad to I/O

dataout to

core

Input delay from pin to

internal cells

1.314 1.211 1.211 2.177 2.340 2.433 2.388 2.508 ns

1.307 1.203 1.203 2.19 2.387 2.540 2.430 2.545 ns

0.437 0.402 0.402 0.747 0.820 0.880 0.834 0.873 ns

Input delay from pin to Pad to I/O

input register

I/O output

pad

Delay from output

Input delay from

dual-purpose clock pin clock

to fan-out destinations network

Pad to global

0.693 0.665 0.665 1.200 1.379 1.532 1.393 1.441 ns

Notes to Table 1–42:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Table 1–43. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices ^{(1), (2)}