EP4CE15F23C6N 参数 Datasheet PDF下载

型号：	EP4CE15F23C6N
PDF下载：	下载PDF文件查看货源
内容描述：	本节列出了I / O的漏电流，引脚电容，片上端接（ OCT）耐受性，以及Cyclone IV器件总线保持规范。 [This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT) tolerance, and bus hold specifications for Cyclone IV devices.]
分类和应用：	现场可编程门阵列可编程逻辑栅LTE时钟
文件页数/大小：	42 页 / 678 K
品牌：	ALTERA [ ALTERA CORPORATION ]

1–30

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (3)}(Part 2 of 2)

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max

(2)

t_LOCK

—

Notes to Table 1–32:

(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX

devices.

(2) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and

A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (2), (4)}

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

200

400

—

155.5

311

—

155.5

311

—

155.5

311

—

132.5 MHz

265 MHz

265 Mbps

f_HSCLK(input

clock

frequency)

100

—

400 100

400 80

400 70

400 40

400 20

400 10

311 100

311

—

311

—

311

—

Device

operation in

Mbps

t_DUTY

—

TCCS

200

Output jitter

(peak to peak)

—

500

—

500

—

550

—

600

—

700

20 – 80%,

t_RISE

C_LOAD

5 pF

—

500

—

500

—

500

—

500

—

500

—

20 – 80%,

t_FALL

C_LOAD

5 pF

—

500

—

500

—

500

—

500

—

500

—

(3)

t_LOCK

—

Notes to Table 1–33:

(1) Applicable for true and emulated mini-LVDS transmitter.

(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at

the output pin of all I/O banks.

Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the

output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.

(3) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and

A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Cyclone IV Device Handbook,

Volume 3

December 2013 Altera Corporation

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EP4CE15F23C6N 参数 Datasheet PDF下载

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