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EP3C25F256C8NES 参数 Datasheet PDF下载

EP3C25F256C8NES图片预览
型号: EP3C25F256C8NES
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 24624 CLBs, 472.5MHz, PBGA256, 17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 367 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Cyclone III Device Data Sheet  
1–11  
Electrical Characteristics  
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices  
Symbol  
Parameter  
Conditions  
Minimum  
200  
Typical  
Maximum  
Unit  
V
CCIO = 3.3 V  
VCCIO = 2.5 V  
VCCIO = 1.8 V  
VCCIO = 1.5 V  
mV  
mV  
mV  
mV  
200  
Hysteresis for Schmitt trigger  
input  
VSCHMITT  
140  
110  
I/O Standard Specifications  
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH  
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards  
supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O  
standard specifications for Cyclone III devices.  
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications (Note 1), (2)  
V
CCIO (V)  
Typ  
VIL (V)  
Max  
VIH (V)  
Max  
VOL (V)  
VOH (V)  
IOL  
IOH  
I/O Standard  
(mA)  
(mA)  
Min  
Max  
3.465  
3.465  
Min  
Min  
1.7  
1.7  
1.7  
1.7  
Max  
0.45  
0.2  
Min  
2.4  
3.3-V LVTTL (3)  
3.135 3.3  
0.8  
0.8  
0.8  
0.8  
3.6  
4
2
–4  
–2  
3.3-V LVCMOS (3) 3.135 3.3  
3.6  
VCCIO – 0.2  
2.4  
3.0-V LVTTL (3)  
2.85  
3.0  
3.0  
3.15 –0.3  
3.15 –0.3  
VCCIO + 0.3  
VCCIO + 0.3  
0.45  
0.2  
4
–4  
3.0-V LVCMOS (3) 2.85  
VCCIO – 0.2  
0.1  
–0.1  
2.5-V LVTTL and  
LVCMOS (3)  
2.375 2.5  
1.71 1.8  
1.425 1.5  
2.625 –0.3  
1.89 –0.3  
1.575 –0.3  
1.26 –0.3  
0.7  
1.7  
V
CCIO + 0.3  
0.4  
2.0  
1
2
–1  
–2  
1.8-V LVTTL and  
LVCMOS  
0.35 * 0.65 *  
VCCIO VCCIO  
2.25  
0.45  
VCCIO – 0.45  
0.35 * 0.65 *  
VCCIO VCCIO  
1.5-V LVCMOS  
1.2-V LVCMOS  
3.0-V PCI  
VCCIO + 0.3 0.25 * VCCIO 0.75 * VCCIO  
VCCIO + 0.3 0.25 * VCCIO 0.75 * VCCIO  
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO  
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO  
2
–2  
0.35 * 0.65 *  
VCCIO  
1.14  
2.85  
2.85  
1.2  
3.0  
3.0  
2
–2  
VCCIO  
0.3 *  
VCCIO  
0.5 *  
VCCIO  
3.15  
3.15  
1.5  
1.5  
–0.5  
–0.5  
0.35*  
VCCIO  
0.5 *  
VCCIO  
3.0-V PCI-X  
Notes to Table 1–13:  
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/OStandard”  
in “Glossary” on page 1–27.  
(2) AC load CL = 10 pF.  
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III  
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.  
© January 2010 Altera Corporation  
Cyclone III Device Handbook, Volume 2