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EP3C55F484C6N 参数 Datasheet PDF下载

EP3C55F484C6N图片预览
型号: EP3C55F484C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 55856 CLBs, 472.5MHz, 55856-Cell, CMOS, PBGA484, 23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 367 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Cyclone III Device Data Sheet  
1–9  
Electrical Characteristics  
Example 1–1 shows you the example to calculate the change of 50 Ω I/O impedance  
from 25°C at 3.0 V to 85°C at 3.15 V:  
Example 1–1.  
ΔRV = (3.15 – 3) × 1000 × –0.026 = –3.83  
ΔRT = (85 – 25) × 0.262 = 15.72  
Because ΔRV is negative,  
MFV = 1 / (3.83/100 + 1) = 0.963  
Because ΔRT is positive,  
MFT = 15.72/100 + 1 = 1.157  
MF = 0.963 × 1.157 = 1.114  
Rfinal = 50 × 1.114 = 55.71 Ω  
Pin Capacitance  
Table 1–9 lists the pin capacitance for Cyclone III devices.  
Table 1–9. Cyclone III Devices Pin Capacitance  
Typical – Typical –  
Symbol  
Parameter  
Unit  
QFP  
FBGA  
CIOTB  
CIOLR  
Input capacitance on top/bottom I/O pins  
Input capacitance on left/right I/O pins  
7
6
5
pF  
pF  
7
Input capacitance on left/right I/O pins with dedicated  
LVDS output  
CLV DSLR  
8
21  
7
21  
pF  
pF  
pF  
Input capacitance on left/right dual-purpose VREF pin  
when used as VREF or user I/O pin  
C
C
VREFLR (1)  
VREFTB (1)  
Input capacitance on top/bottom dual-purpose VREFpin  
when used as VREF or user I/O pin  
23 (2)  
23 (2)  
Input capacitance on top/bottom dedicated clock input  
pins  
CCLKTB  
CCLKLR  
7
6
6
5
pF  
pF  
Input capacitance on left/right dedicated clock input pins  
Notes to Table 1–9:  
(1) When VREF pin is used as regular input or output, a reduced performance of toggle rate and tCO is expected due to  
higher pin capacitance.  
(2) CVREFTB for EP3C25 is 30 pF.  
© January 2010 Altera Corporation  
Cyclone III Device Handbook, Volume 2  
 
 
 
 
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