3–2
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Table 3–1 lists the features supported by the M9K memory
Table 3–1. Summary of M9K Memory Features
Feature
M9K Blocks
8192 × 1
4096 × 2
2048 × 4
1024 × 8
Configurations (depth × width)
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
Parity bits
v
Byte enable
v
Packed mode
v
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
v
v
v
v
(1)
Embedded shift register mode
v
ROM mode
v
(1)
FIFO buffer
v
Simple dual-port mixed width support
v
(2)
True dual-port mixed width support
v
v
Memory initialization file (.mif)
Mixed-clock mode
v
Power-up condition
Outputs cleared
Register asynchronous clears
Latch asynchronous clears
Write or read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Notes to Table 3–1:
Read address registers and output registers only
Output latches only
Write and read: Rising clock edges
Outputs set to Old Data or New Data
Outputs set to Old Data or Don’t Care
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
logic.
(2) Width modes of ×32 and ×36 are not available.
f
For information about the number of M9K memory blocks for the Cyclone III device
family, refer to the Cyclone III Device Family Overview chapter.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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