Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–39
shows the timing waveform for a PS configuration when using an
external host device as an external host.
Figure 9–17. PS Configuration Timing Waveform
t
CF2ST1
t
CFG
nCONFIG
nSTATUS
(2)
CONF_DONE
(3)
t
CF2CD
t
CF2CK
t
STATUS
t
CF2ST0
t
t
ST2CK
CLK
t
CH
t
CL
DCLK
(4)
t
DH
DATA[0]
Bit 0
Bit 1 Bit 2 Bit 3
t
DSU
Bit
n
(5)
User Mode
User I/O Tri-stated
with
internal pull-up resistor
INIT_DONE
t
CD2UM
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG, nSTATUS,
and
CONF_DONE
are at logic-high levels. When
nCONFIG
is pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds
nSTATUS
low during POR delay.
(3) After power-up, before and during configuration,
CONF_DONE
is low.
(4) In user mode, drive
DCLK
either high or low when using the PS configuration scheme, whichever is more convenient.
When using the AS configuration scheme,
DCLK
is a Cyclone III device family output pin and must not be driven
externally.
(5) Do not leave the
DATA[0]
pin floating after configuration. Drive it high or low, whichever is more convenient.
lists the PS configuration timing parameters for Cyclone III device family.
Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 1 of 2)
Symbol
t
CF2CD
t
CF2ST0
t
CFG
t
STATUS
t
CF2ST1
t
CF2CK
t
ST2CK
t
DSU
t
DH
t
CH
t
CL
t
CLK
f
MAX
t
CD2UM
t
CD2CU
Parameter
Minimum
—
—
500
45
—
800
2
5
0
3.2
3.2
7.5
—
Maximum
500
500
—
800
800
—
—
—
—
—
—
—
100
—
Unit
ns
ns
ns
s
s
s
s
ns
ns
ns
ns
ns
MHz
s
—
nCONFIG
low to
CONF_DONE
low
nCONFIG
low to
nSTATUS
low
nCONFIG
low pulse width
nSTATUS
low pulse width
nCONFIG
high to
nSTATUS
high
nCONFIG
high to first rising edge on
DCLK
nSTATUS
high to first rising edge of
DCLK
Data setup time before rising edge on
DCLK
Data hold time after rising edge on
DCLK
DCLK
high time
DCLK
low time
DCLK
period
DCLK
frequency
CONF_DONE
high to user mode
CONF_DONE
high to
CLKUSR
enabled
300
4 × maximum
DCLK
period
650
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
