Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–31
shows the AP configuration with multiple bus masters.
Figure 9–11. AP Configuration with Multiple Bus Masters
Other Master Device
(6)
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
I/O
(7)
nCONFIG
(8)
VCCIO
(1)
VCCIO
(1)
VCCIO
(1)
10 k
10 k
10 k
nSTATUS
nCE
10 k
GND
nCEO
DCLK
(5)
nRESET
FLASH_nCE
nOE
nAVD
MSEL[3..0]
nWE
I/O
(4)
DATA[15..0]
(5)
PADD[23..0]
CONF_DONE
nCONFIG
(2)
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
(3)
Micron P30/P33 Flash
Cyclone III Master Device
Notes to
(1) Connect the pull-up resistors to the V
CCIO
supply of the bank in which the pin resides.
(2) The
nCEO
pin is left unconnected or used as a user I/O pin when it does not feed the
nCE
pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect
MSEL[3..0],
refer to
Connect the MSEL pins directly to V
CCA
or GND.
(4) The AP configuration ignores the
WAIT
signal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the
WAIT
signal from the Micron P30 or P33 flash.
(5) When cascading Cyclone III devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave devices
for
DATA[15..0]
and
DCLK.
All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit
the maximum overshoot equation outlined in
(6) The other master device must fit the maximum overshoot equation outlined in
(7) The other master device can control the AP configuration bus by driving the nCE pin to high with an output high on the I/O pin.
(8) The other master device can pulse
nCONFIG
if it is under system control rather than tied to V
CCIO
.
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
