9–28
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
The following are the configurations for the
DATA[15..0]
bus in a multi-device AP
configuration:
■
■
Byte-wide multi-device AP configuration
Word-wide multi-device AP configuration
Byte-Wide Multi-Device AP Configuration
The simpler method for multi-device AP configuration is the byte-wide multi-device
AP configuration. In the byte-wide multi-device AP configuration, the LSB of the
DATA[7..0]pin
from the flash and master device (set to the AP configuration scheme)
is connected to the slave devices set to the FPP configuration scheme, as shown in
Figure 9–9. Byte-Wide Multi-Device AP Configuration
VCCIO
(1)
VCCIO
(1)
10 k
Ω
10 k
Ω
VCCIO
(1)
10 k
Ω
VCCIO
(2)
VCCIO
(2)
10 k
Ω
10 k
Ω
nSTATUS
nSTATUS
nCONFIG
nCONFIG
CONF_DONE
CONF_DONE
nCONFIG
nSTATUS
nCE
GND
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O
(5)
DATA[15..0]
PADD[23..0]
nCEO
nCE
nCEO
nCE
nCEO
CONF_DONE
N.C.
(3)
MSEL[3..0]
(4)
DQ[7..0]
MSEL[3..0]
DATA[7..0]
DCLK
(4)
DQ[7..0]
MSEL[3..0]
DATA[7..0]
DCLK
(4)
Micron P30/P33 Flash
Cyclone III Master Device
Cyclone III Slave Device
Cyclone III Slave Device
Buffers (6)
Notes to
(1) Connect the pull-up resistors to the V
CCIO
supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the V
CCIO
supply voltage of the I/O bank in which the
nCE
pin resides.
(3) The
nCEO
pin is left unconnected or used as a user I/O pin when it does not feed the
nCE
pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
devices in FPP mode. To connect
MSEL[3..0]
for the master device in AP mode and the slave devices in FPP mode, refer to
Connect the MSEL pins directly to V
CCA
or GND.
(5) The AP configuration ignores the
WAIT
signal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the
WAIT
signal from the Micron P30 or P33 flash.
(6) Connect the repeater buffers between the master device and slave devices for
DATA[15..0]
and
DCLK.
All I/O inputs must maintain a maximum
AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
