9–14
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
In a single-device AS configuration, the maximum board loading and board trace
length between the supported serial configuration device and the Cyclone III device
family must follow the recommendations in
The
DCLK
generated by the Cyclone III device family controls the entire configuration
cycle and provides timing for the serial interface. Cyclone III device family uses a 40-
MHz internal oscillator to generate
DCLK.
There are some variations in the internal
oscillator frequency because of the process, voltage, and temperature conditions in
Cyclone III device family. The internal oscillator is designed to ensure that its
maximum frequency is guaranteed to meet the EPCS device specifications.
1
EPCS1 does not support Cyclone III device family because of its insufficient memory
capacity.
lists the AS
DCLK
output frequency for Cyclone III device family.
Table 9–8. AS DCLK Output Frequency
Oscillator
40 MHz
Minimum
20
Typical
30
Maximum
40
Unit
MHz
In the AS configuration scheme, the serial configuration device latches input and
control signals on the rising edge of
DCLK
and drives out configuration data on the
falling edge. Cyclone III device family drives out control signals on the falling edge of
DCLK
and latch configuration data on the falling edge of
DCLK.
In configuration mode, the Cyclone III device family enables the serial configuration
device by driving the
nCSO
output pin low, which connects to the
nCS
pin of the
configuration device. The Cyclone III device family uses the
DCLK
and
DATA[1]pins
to
send operation commands and read address signals to the serial configuration device.
The configuration device provides data on its
DATA
pin, which connects to the
DATA[0]
input of the Cyclone III device family.
After all the configuration bits are received by the Cyclone III device family, it releases
the open-drain
CONF_DONE
pin, which is pulled high by an external 10-k resistor.
Initialization begins only after the
CONF_DONE
signal reaches a logic-high level. All AS
configuration pins (DATA[0],
DCLK, nCSO,
and
DATA[1])
have weak internal pull-up
resistors that are always active. After configuration, these pins are set as input tri-
stated and are driven high by weak internal pull-up resistors. The
CONF_DONE
pin must
have an external 10-k pull-up resistor for the device to initialize.
The timing parameters for AS mode are not listed here because the t
CF2CD
, t
CF2ST0
, t
CFG
,
t
STATUS
, t
CF2ST1
, and t
CD2UM
timing parameters are identical to the timing parameters
for PS mode listed in
Multi-Device AS Configuration
You can configure multiple Cyclone III device family using a single serial
configuration device. You can cascade multiple Cyclone III device family using the
chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in the chain must
have its
nCE
pin connected to GND. You must connect its
nCEO
pin to the
nCE
pin of the
next device in the chain. Use an external 10-k pull-up resistor to pull the
nCEO
signal
high to its V
CCIO
level to help the internal weak pull-up resistor. When the first device
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
