Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface
7–3
lists which I/O bank supports these I/O standards in the Cyclone III device
family.
Table 7–1. Differential I/O Standards Supported in Cyclone III Device Family I/O Banks
Differential I/O Standards
I/O Bank Location
1,2,5,6
All
1,2,5,6
RSDS
3, 4, 7, 8
All
mini-LVDS
PPDS
BLVDS
LVPECL
External Resistor
Network at
Transmitter
Not Required
Three Resistors
Not Required
Three Resistors
Single Resistor
Not Required
Three Resistors
Not Required
Three Resistors
Single Resistor
NA
NA
NA
NA
NA
NA
Transmitter (TX)
Receiver (RX)
LVDS
Yes
Yes
Yes
Not
Supported
Not
Supported
Not
Supported
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1,2,5,6
All
1,2,5,6
All
All
All
All
All
All
All
All
Yes
Yes
Yes
Not
Supported
Yes
Yes
Yes
Yes
Yes
Differential SSTL-2
Differential SSTL-18
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
Notes to
(1) Transmitter and Receiver F
MAX
depend on system topology and performance requirement.
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
You can use I/O pins and internal logic to implement a high-speed differential
interface in the Cyclone III device family. The Cyclone III device family does not
contain dedicated serialization or deserialization circuitry. Therefore, shift registers,
internal phase-locked loops (PLLs), and I/O cells are used to perform
serial-to-parallel conversions on incoming data and parallel-to-serial conversion on
outgoing data. The differential interface data serializers and deserializers (SERDES)
are automatically constructed in the core logic elements (LEs) with the Quartus
®
II
software ALTLVDS megafunction.
December 2011
Altera Corporation
Cyclone III Device Handbook
Volume 1