7–2
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface
shows the I/O banks of the Cyclone III device family.
Figure 7–1. Cyclone III Device Family I/O Banks
I/O banks 7 and 8 also support the
HSTL-12 Class II I/O standard
I/O Bank 8
I/O Bank 7
All I/O Banks Support:
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI/PCI-X
(1)
LVDS
RSDS
(2)
BLVDS
(5)
mini-LVDS
(2)
PPDS
(2)
LVPECL
(3)
SSTL-2 Class I and II
SSTL-18 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I
Differential SSTL-2
(4)
Differential SSTL-18
(4)
Differential HSTL-18
(4)
DIfferential HSTL-15
(4)
Differential HSTL-12
(4)
I/O Bank 2
I/O Bank 1
I/O Bank 3
I/O Bank 4
I/O banks 3 and 4 also support the
HSTL-12 Class II I/O standard
Notes to
(1) The PCI-X I/O standard does not meet the IV curve requirement at the linear region.
(2) The RSDS, mini-LVDS, and PPDS I/O standards are only supported on output pins. These I/O standards are not supported on input pins.
(3) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported on output pins.
(4) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on dedicated clock input pins and PLL
output clock pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O
standards.
(5) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses LVDS input buffer.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
I/O Bank 5
I/O Bank 6
ALTERA [ ALTERA CORPORATION ]
