Stratix II Architecture
Table 2–10 shows the enhanced PLL and fast PLL features in Stratix II
devices.
Table 2–10. Stratix II PLL Features
Feature
Enhanced PLL
Fast PLL
Clock multiplication and division
Phase shift
m/(n × post-scale counter) (1)
m/(n × post-scale counter) (2)
Down to 125-ps increments (3), (4)
Down to 125-ps increments (3), (4)
Clock switchover
v
v (5)
v
PLL reconfiguration
v
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
v
v
v
v
v
4
6
Three differential/six single-ended
(6)
One single-ended or differential
(7), (8)
Notes to Table 2–10:
(1) For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty
cycle.
(2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
(4) For degree increments, Stratix II devices can shift all output frequencies in increments of at least 45. Smaller degree
increments are possible depending on the frequency and divide parameters.
(5) Stratix II fast PLLs only support manual clock switchover.
(6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
(7) If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
(8) Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input
per PLL.
Altera Corporation
May 2007
2–59
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
