PLLs & Clock Networks
1
When using the global or regional clock control blocks in
Stratix II devices to select between multiple clocks or to enable
and disable clock networks, be aware of possible narrow pulses
or glitches when switching from one clock signal to another. A
glitch or runt pulse has a width that is less than the width of the
highest frequency input clock signal. To prevent logic errors
within the FPGA, Altera recommends that you build circuits
that filter out glitches and runt pulses.
Figures 2–37 through 2–39 show the clock control block for the global
clock, regional clock, and PLL external clock output, respectively.
Figure 2–37. Global Clock Control Blocks
CLKp
Pins
PLL Counter
Outputs
2
2
CLKn
Pin
Internal
Logic
CLKSELECT[1..0]
2
(1)
Static Clock Select (2)
This multiplexer supports
User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2–37:
(1) These clock select signals can be dynamically controlled through internal logic
when the device is operating in user mode.
(2) These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
2–54
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
