Timing Model
Table 5–39. DSP Block Internal Timing Microparameters (Part 1 of 2)
-3 Speed
Grade (1)
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
Max
(3)
Min
Max
(3)
Min
(4)
Min
(3)
Max
Max
tSU
Input, pipeline, and
output register setup
time before clock
50
52
57
57
67
ps
ps
ps
tH
Input, pipeline, and
output register hold
time after clock
180
189
206
206
241
0
tCO
Input, pipeline, and
output register clock-
to-output delay
0
0
0
0
0
0
0
0
tINREG2PIPE9
tINREG2PIPE18
tINREG2PIPE36
Input register to DSP 1,312 2,030 1,312 2,030 1,250 2,334 1,312 2,720 ps
block pipeline register
in 9 × 9-bit mode
1,312
Input register to DSP 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 ps
block pipeline register
in 18 × 18-bit mode
1,302
Input register to DSP 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 ps
block pipeline register
in 36 × 36-bit mode
1,302
tPIPE2OUTREG2ADD DSP block pipeline
register to output
924 1,450 924 1,522 880 1,667 924 1,943 ps
924
register delay in two-
multipliers adder
mode
tPIPE2OUTREG4ADD DSP block pipeline
register to output
1,134 1,850 1,134 1,942 1,080 2,127 1,134 2,479 ps
1,134
register delay in four-
multipliers adder
mode
tPD9
Combinational input
to output delay for
9 × 9
2,100 2,880 2,100 3,024 2,000 3,312 2,100 3,859 ps
2,100
tPD18
tPD36
tCLR
Combinational input
to output delay for
18 × 18
2,110 2,990 2,110 3,139 2,010 3,438 2,110 4,006 ps
2,110
Combinational input
to output delay for
36 × 36
2,939 4,450 2,939 4,672 2,800 5,117 2,939 5,962 ps
2,939
Minimum clear pulse 2,212
width
2,322
2,543
2,543
2,964
ps
5–36
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
