DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 6 of 6)
Note (1)
Resources Used
Performance
-3
-3
TriMatrix
ALUTs Memory
Blocks
-4
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
Larger
designs
8-bit, 1024-point,
7385
60
60
36
359.58 352.98 312.01 278.00 MHz
quadrant output, four
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
8-bit, 1024-point,
6601
48
371.88 355.74 327.86 277.62 MHz
quadrant output, four
parallel FFT engines,
buffered burst, four
multipliers and two
adders FFT function
Notes for Table 5–36:
(1) These design performance numbers were obtained using the Quartus II software version 5.0 SP1.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) This application uses registered inputs and outputs.
(5) This application uses registered multiplier input and output stages within the DSP block.
(6) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
(7) This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
(8) This application uses the same clock source that is globally routed and connected to ports A and B.
(9) This application uses locally routed clocks or differently sourced clocks for ports A and B.
Altera Corporation
May 2007
5–33
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
