DC & Switching Characteristics
Table 5–35. Timing Measurement Methodology for Input Pins (Part 2 of 2)
Notes (1)–(4)
Measurement Conditions
I/O Standard
Measurement Point
VCCIO (V)
VREF (V)
VMEAS (V)
Edge Rate (ns)
1.8-V HSTL Class II
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
2.325
3.135
0.830
0.688
0.688
0.570
1.163
1.163
0.830
0.830
0.688
0.688
0.830
0.830
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
0.100
0.400
0.100
0.83
0.6875
0.6875
0.570
1.1625
1.1625
0.83
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
0.83
0.6875
0.6875
0.83
0.83
1.1625
1.1625
1.5675
HyperTransport
LVPECL
Notes to Table 5–35:
(1) Input buffer sees no load at buffer input.
(2) Input measuring point at buffer input is 0.5 × VCCIO
.
(3) Output measuring point is 0.5 × VCC at internal node.
(4) Input edge rate is 1 V/ns.
(5) Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple
(6) VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
Performance
Table 5–36 shows Stratix II performance for some common designs. All
performance values were obtained with the Quartus II software
compilation of library of parameterized modules (LPM), or MegaCore®
functions for the finite impulse response (FIR) and fast Fourier transform
(FFT) designs.
Altera Corporation
May 2007
5–27
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
