欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP2S90F1020C4N的Datasheet PDF文件第119页浏览型号EP2S90F1020C4N的Datasheet PDF文件第120页浏览型号EP2S90F1020C4N的Datasheet PDF文件第121页浏览型号EP2S90F1020C4N的Datasheet PDF文件第122页浏览型号EP2S90F1020C4N的Datasheet PDF文件第124页浏览型号EP2S90F1020C4N的Datasheet PDF文件第125页浏览型号EP2S90F1020C4N的Datasheet PDF文件第126页浏览型号EP2S90F1020C4N的Datasheet PDF文件第127页  
Configuration & Testing  
1
An encryption configuration file is the same size as a non-  
encryption configuration file. When using a serial configuration  
scheme such as passive serial (PS) or active serial (AS),  
configuration time is the same whether or not the design  
security feature is enabled. If the fast passive parallel (FPP)  
scheme us used with the design security or decompression  
feature, a 4× DCLKis required. This results in a slower  
configuration time when compared to the configuration time of  
an FPGA that has neither the design security, nor  
decompression feature enabled. For more information about  
this feature, refer to AN 341: Using the Design Security Feature in  
Stratix II Devices. Contact your local Altera sales representative  
to request this document.  
Device Configuration Data Decompression  
Stratix II FPGAs support decompression of configuration data, which  
saves configuration memory space and time. This feature allows you to  
store compressed configuration data in configuration devices or other  
memory, and transmit this compressed bit stream to Stratix II FPGAs.  
During configuration, the Stratix II FPGA decompresses the bit stream in  
real time and programs its SRAM cells.  
Stratix II FPGAs support decompression in the FPP (when using a  
MAX II device/microprocessor and flash memory), AS and PS  
configuration schemes. Decompression is not supported in the PPA  
configuration scheme nor in JTAG-based configuration.  
Remote System Upgrades  
Shortened design cycles, evolving standards, and system deployments in  
remote locations are difficult challenges faced by modern system  
designers. Stratix II devices can help effectively deal with these  
challenges with their inherent re-programmability and dedicated  
circuitry to perform remote system updates. Remote system updates help  
deliver feature enhancements and bug fixes without costly recalls, reduce  
time to market, and extend product life.  
Stratix II FPGAs feature dedicated remote system upgrade circuitry to  
facilitate remote system updates. Soft logic (Nios® processor or user logic)  
implemented in the Stratix II device can download a new configuration  
image from a remote location, store it in configuration memory, and direct  
the dedicated remote system upgrade circuitry to initiate a  
reconfiguration cycle. The dedicated circuitry performs error detection  
during and after the configuration process, recovers from any error  
condition by reverting back to a safe configuration image, and provides  
Altera Corporation  
May 2007  
3–9  
Stratix II Device Handbook, Volume 1  
 复制成功!