3. Configuration & Testing
SII51003-4.2
All Stratix® II devices provide Joint Test Action Group (JTAG)
boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1. JTAG boundary-scan testing can be performed either before
or after, but not during configuration. Stratix II devices can also use the
JTAG port for configuration with the Quartus® II software or hardware
using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
IEEE Std. 1149.1
JTAG Boundary-
Scan Support
Stratix II devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode through the CONFIG_IO instruction. You can use this capability
for JTAG testing before configuration when some of the Stratix II pins
drive or receive from other devices on the board using voltage-referenced
standards. Because the Stratix II device may not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those
I/O standards via JTAG allows you to fully test I/O connections to other
devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS,
and TCK, and one optional pin, TRST. The TCKpin has an internal weak
pull-down resistor, while the TDI,TMSand TRSTpins have weak internal
pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The
TDO output pin is powered by the VCCIO power supply of bank 4.
Stratix II devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap® II embedded logic analyzer. Stratix II
devices support the JTAG instructions shown in Table 3–1.
1
Stratix II, Stratix, Cyclone® II, and Cyclone devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II, or Cyclone devices are in the 18th of further position,
they fail configuration. This does not affect SignalTap II.
The Stratix II device instruction register length is 10 bits and the
USERCODEregister length is 32 bits. Tables 3–2 and 3–3 show the
boundary-scan register length and device IDCODE information for
Stratix II devices.
Altera Corporation
May 2007
3–1
ALTERA [ ALTERA CORPORATION ]
