JTAG Configuration
Figure 13–23. JTAG Configuration of a Single Device Using a Microprocessor
Cyclone II FPGA
Memory
(3)
nCE
DATA
ADDR
(2)
(2)
nCEO
(4)
MSEL1
MSEL0
(1)
V
(2)
(2)
(2)
nCONFIG
DATA0
DCLK
TDI
CC
(1)
V
CC
10 kΩ
10 kΩ
TCK
TMS
TDO
nSTATUS
Microprocessor
CONF_DONE
Notes to Figure 13–23:
(1) The pull-up resistor should be connected to a supply that provides an acceptable
input signal for all devices in the chain.
(2) Connect the nCONFIGand MSEL[1..0]pins to support a non-JTAG
configuration scheme. If only JTAG configuration is used, connect the nCONFIG
pin to VCC, and the MSEL[1..0]pins to ground. In addition, pull DCLKand
DATA0to either high or low, whichever is convenient on your board.
(3) nCEmust be connected to GND or driven low for successful JTAG configuration.
(4) If using an EPCS4 or EPCS1 device, set MSEL[1..0]to 00. See Table 13–4 for more
details.
JTAG Configuration of Multiple Devices
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 13–24 shows multiple device JTAG configuration.
13–58
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
