Configuring Cyclone II Devices
The Enable user-supplied start-up clock (CLKUSR) option can be
turned on in the Quartus II software from the General tab of the Device
& Pin Options dialog box. Supplying a clock on CLKUSRdoes not affect
the configuration process. After all configuration data has been accepted
and CONF_DONEgoes high, Cyclone II devices require 299 clock cycles to
initialize properly and support a CLKUSRfMAX of 100 MHz.
1
If the optional CLKUSRpin is being used and nCONFIGis pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSRcontinues toggling during the time
nSTATUSis low (maximum of 40 µs).
An optional INIT_DONEpin signals the end of initialization and the start
of user mode with a low-to-high transition. By default, the INIT_DONE
output is disabled. You can enable the INIT_DONEoutput by turning on
the Enable INIT_DONE output option in the Quartus II software. If you
use the INIT_DONEpin, an external 10-kΩpull-up resistor pulls the pin
high when nCONFIGis low and during the beginning of configuration.
Once the optional bit to enable INIT_DONEis programmed into the
device (during the first frame of configuration data), the INIT_DONEpin
transitions low. When initialization is complete, the INIT_DONEpin is
released and pulled high. The MAX II device must be able to detect this
low-to-high transition, which signals the FPGA has entered user mode.
If you want to use the INIT_DONEpin as a user I/O pin, you should wait
for the maximum value of tCD2UM (see Table 13–7) after the CONF_DONE
signal transitions high so to ensure the Cyclone II device has been
initialized properly and is in user mode.
Make sure the MAX II device does not drive the CONF_DONEsignal low
during configuration, initialization, and before the device enters user
mode.
User Mode
When initialization is complete, the Cyclone II device enters user mode.
In user mode, the user I/O pins no longer have pull-up resistors and
function as assigned in your design.
To ensure DCLKand DATA0are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
which ever is convenient on your PCB. The Cyclone II device DATA0pin
is not available as a user I/O pin after configuration.
When the FPGA is in user mode, you can initiate a reconfiguration by
transitioning the nCONFIGpin low-to-high. The nCONFIGpin must be
low for at least 2 µs. When the nCONFIGtransitions low, the Cyclone II
Altera Corporation
February 2007
13–25
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
