Configuring Cyclone II Devices
Figure 13–9. Single Device PS Configuration Using an External Host
Memory
V
. (1)
V
. (1)
CC
CC
V
CC
ADDR
DATA0
Cyclone II Device
10 kΩ
10 kΩ
MSEL0
MSEL1
CONF_DONE
nSTATUS
nCE
GND
N.C. (2)
External Host
(MAX II Device or
Microprocessor)
GND
nCEO
DATA0
nCONFIG
DCLK
Notes to Figure 13–9:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC should be high
enough to meet the VIH specification of the I/O on the device and the external host.
(2) The nCEOpin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCEpin.
Upon power-up, the Cyclone II device goes through a POR, which lasts
approximately 100 ms. During POR, the device resets, holds nSTATUS
low, and tri-states all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins continue to be tri-stated.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Cyclone II Device Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization.
Reset Stage
While the Cyclone II device’s nCONFIGor nSTATUSpins are low, the
device is in reset. To initiate configuration, the MAX II device must
transition the Cyclone II nCONFIGpin from low to high.
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
When the Cyclone II nCONFIGpin transitions high, the Cyclone II device
comes out of reset and releases the open-drain nSTATUSpin, which is
then pulled high by an external 10-kΩpull-up resistor. Once nSTATUSis
released, the FPGA is ready to receive configuration data and the MAX II
device can start the configuration at any time.
Altera Corporation
February 2007
13–23
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
