Cyclone II Architecture
Figure 2–21. Row I/O Block Connection to the Interconnect
R4 & R24 Interconnects
C4 Interconnects
I/O Block Local
Interconnect
35 Data and
Control Signals
from Logic Array (1)
35
LAB
Row
I/O Block
io_datain0[4..0]
io_datain1[4..0] (2)
Direct Link
Interconnect
from Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
Row I/O Block
Contains up to
Five IOEs
io_clk[5..0]
LAB Local
Interconnect
Notes to Figure 2–21:
(1) The 35 data and control signals consist of five data out lines, io_dataout[4..0], five output enables,
io_coe[4..0], five input clock enables, io_cce_in[4..0], five output clock enables, io_cce_out[4..0],
five clocks, io_cclk[4..0], five asynchronous clear signals, io_caclr[4..0], and five synchronous clear
signals, io_csclr[4..0].
(2) Each of the five IOEs in the row I/O block can have two io_datain (combinational or registered) inputs.
Altera Corporation
February 2007
2–39
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
