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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

EP2C50A15Q324C6ES图片预览
型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Embedded Memory  
Each M4K block can implement various types of memory with or without  
parity, including true dual-port, simple dual-port, and single-port RAM,  
ROM, and first-in first-out (FIFO) buffers. The M4K blocks support the  
following features:  
4,608 RAM bits  
250-MHz performance  
True dual-port memory  
Simple dual-port memory  
Single-port memory  
Byte enable  
Parity bits  
Shift register  
FIFO buffer  
ROM  
Various clock modes  
Address clock enable  
1
Violating the setup or hold time on the memory block address  
registers could corrupt memory contents. This applies to both  
read and write operations.  
Table 2–5 shows the capacity and distribution of the M4K memory blocks  
in each Cyclone II device.  
Table 2–5. M4K Memory Capacity & Distribution in Cyclone II Devices  
Device  
M4K Columns  
M4K Blocks  
Total RAM Bits  
EP2C5  
2
2
2
2
3
3
5
26  
36  
119,808  
165,888  
239,616  
239,616  
483,840  
594,432  
1,152,000  
EP2C8  
EP2C15  
EP2C20  
EP2C35  
EP2C50  
EP2C70  
52  
52  
105  
129  
250  
2–28  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007  
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