Timing Specifications
Table 5–15. Cyclone II Performance (Part 4 of 4)
Resources Used
Performance (MHz)
–7 –7
Speed Speed
Grade Grade
M4K
LEs Memory
Blocks
–6
Speed
Grade
–8
Speed
Grade
Applications
DSP
Blocks
(6)
(7)
Larger
8-bit, 1024 pt, Quad Output,
8053
60
36
200.0
200.0
195.0 149.23 163.02
Designs 4 Parallel FFT Engines, Buffered
Burst, 3 Mults/5 Adders FFT
function
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 4 Mults/2 Adders FFT
function
7453
60
48
195.0 151.28 163.02
Notes to Table 5–15 :
(1) This application uses registered inputs and outputs.
(2) This application uses registered multiplier input and output stages within the DSP block.
(3) This application uses the same clock source for both A and B ports.
(4) This application uses independent clock sources for A and B ports.
(5) This application uses PLL clock outputs that are globally routed to connect and drive M4K clock ports. Use of
non-PLL clock sources or local routing to drive M4K clock ports may result in lower performance numbers than
shown here. Refer to the Quartus II timing report for actual performance numbers.
(6) These numbers are for commercial devices.
(7) These numbers are for automotive devices.
Internal Timing
Refer to Tables 5–16 through 5–19 for the internal timing parameters.
Table 5–16. LE_FF Internal Timing Microparameters (Part 1 of 2)
–6 Speed Grade (1)
–7 Speed Grade (2)
–8 Speed Grade (3)
Parameter
Unit
Min
Max
Min
Max
Min
Max
TSU
–36
—
—
—
–40
–38
306
286
135
141
244
217
—
—
–40
–40
306
306
135
141
244
244
—
—
ps
ps
ps
ps
ps
ps
ps
ps
TH
266
—
—
—
—
—
—
—
TCO
TCLR
141
—
250
—
277
—
304
—
191
—
—
—
—
—
—
—
5–18
Altera Corporation
February 2008
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
