欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2C50A15F324I6ES 参数 Datasheet PDF下载

EP2C50A15F324I6ES图片预览
型号: EP2C50A15F324I6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第65页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第66页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第67页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第68页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第70页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第71页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第72页浏览型号EP2C50A15F324I6ES的Datasheet PDF文件第73页  
Cyclone II Architecture  
I/O Banks  
The I/O pins on Cyclone II devices are grouped together into I/O banks  
and each bank has a separate power bus. EP2C5 and EP2C8 devices have  
four I/O banks (see Figure 2–28), while EP2C15, EP2C20, EP2C35,  
EP2C50, and EP2C70 devices have eight I/O banks (see Figure 2–29).  
Each device I/O pin is associated with one I/O bank. To accommodate  
voltage-referenced I/O standards, each Cyclone II I/O bank has a VREF  
bus. Each bank in EP2C5, EP2C8, EP2C15, EP2C20, EP2C35, and EP2C50  
devices supports two VREF pins and each bank of EP2C70 supports four  
VREF pins. When using the VREF pins, each VREF pin must be properly  
connected to the appropriate voltage level. In the event these pins are not  
used as VREF pins, they may be used as regular I/O pins.  
The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8  
devices and banks 3, 4, 7, and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and  
EP2C70 devices) support all I/O standards listed in Table 2–17, except the  
PCI/PCI-X I/O standards. The left and right side I/O banks (banks 1 and  
3 in EP2C5 and EP2C8 devices and banks 1, 2, 5, and 6 in EP2C15, EP2C20,  
EP2C35, EP2C50, and EP2C70 devices) support I/O standards listed in  
Table 2–17, except SSTL-18 class II, HSTL-18 class II, and HSTL-15 class II  
I/O standards. See Table 2–17 for a complete list of supported I/O  
standards.  
The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8  
devices and banks 3, 4, 7, and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and  
EP2C70 devices) support DDR2 memory up to 167 MHz/333 Mbps and  
QDR memory up to 167 MHz/668 Mbps. The left and right side I/O  
banks (1 and 3 of EP2C5 and EP2C8 devices and 1, 2, 5, and 6 of EP2C15,  
EP2C20, EP2C35, EP2C50, and EP2C70 devices) only support SDR and  
DDR SDRAM interfaces. All the I/O banks of the Cyclone II devices  
support SDR memory up to 167 MHz/167 Mbps and DDR memory up to  
167 MHz/333 Mbps.  
1
DDR2 and QDRII interfaces may be implemented in Cyclone II  
side banks if the use of class I I/O standard is acceptable.  
Altera Corporation  
February 2007  
2–57  
Cyclone II Device Handbook, Volume 1  
 复制成功!