Cyclone II Architecture
Table 2–18. Cyclone II Device LVDS Channels (Part 2 of 2)
Number of LVDS
Channels (1)
Device
Pin Count
EP2C70
672
896
160 (168)
257 (265)
Note to Table 2–18:
(1) The first number represents the number of bidirectional I/O pins which can be
used as inputs or outputs. The number in parenthesis includes dedicated clock
input pin pairs which can only be used as inputs.
You can use I/O pins and internal logic to implement a high-speed I/O
receiver and transmitter in Cyclone II devices. Cyclone II devices do not
contain dedicated serialization or deserialization circuitry. Therefore,
shift registers, internal PLLs, and IOEs are used to perform
serial-to-parallel conversions on incoming data and parallel-to-serial
conversion on outgoing data.
The maximum internal clock frequency for a receiver and for a
transmitter is 402.5 MHz. The maximum input data rate of 805 Mbps and
the maximum output data rate of 640 Mbps is only achieved when DDIO
registers are used. The LVDS standard does not require an input
reference voltage, but it does require a 100-Ωtermination resistor
between the two signals at the input buffer. An external resistor network
is required on the transmitter side.
f
For more information on Cyclone II differential I/O interfaces, see the
High-Speed Differential Interfaces in Cyclone II Devices chapter in Volume 1
of the Cyclone II Device Handbook.
Series On-Chip Termination
On-chip termination helps to prevent reflections and maintain signal
integrity. This also minimizes the need for external resistors in high pin
count ball grid array (BGA) packages. Cyclone II devices provide I/O
driver on-chip impedance matching and on-chip series termination for
single-ended outputs and bidirectional pins.
Altera Corporation
February 2007
2–55
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
