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EP2C8F256C6N 参数 Datasheet PDF下载

EP2C8F256C6N图片预览
型号: EP2C8F256C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 516 CLBs, 500MHz, 8256-Cell, CMOS, PBGA256, LEAD FREE, FBGA-256]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 168 页 / 956 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MultiTrack Interconnect  
R24 row interconnects span 24 LABs and provide the fastest resource for  
long row connections between non-adjacent LABs, M4K memory blocks,  
dedicated multipliers, and row IOEs. R24 row interconnects drive to  
other row or column interconnects at every fourth LAB. R24 row  
interconnects drive LAB local interconnects via R4 and C4 interconnects  
and do not drive directly to LAB local interconnects. R24 interconnects  
can drive R24, R4, C16, and C4 interconnects.  
Column Interconnects  
The column interconnect operates similar to the row interconnect. Each  
column of LABs is served by a dedicated column interconnect, which  
vertically routes signals to and from LABs, M4K memory blocks,  
embedded multipliers, and row and column IOEs. These column  
resources include:  
Register chain interconnects within an LAB  
C4 interconnects traversing a distance of four blocks in an up and  
down direction  
C16 interconnects for high-speed vertical routing through the device  
Cyclone II devices include an enhanced interconnect structure within  
LABs for routing LE output to LE input connections faster using register  
chain connections. The register chain connection allows the register  
output of one LE to connect directly to the register input of the next LE in  
the LAB for fast shift registers. The Quartus II Compiler automatically  
takes advantage of these resources to improve utilization and  
performance. Figure 2–9 shows the register chain interconnects.  
2–12  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007  
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