Contents
Internal Timing ...............................................................................................................................
Cyclone II Clock Timing Parameters ...........................................................................................
Clock Network Skew Adders .......................................................................................................
IOE Programmable Delay .............................................................................................................
Default Capacitive Loading of Different I/O Standards ..........................................................
I/O Delays .......................................................................................................................................
Maximum Input and Output Clock Rate ....................................................................................
High Speed I/O Timing Specifications .......................................................................................
External Memory Interface Specifications ..................................................................................
JTAG Timing Specifications ..........................................................................................................
PLL Timing Specifications ............................................................................................................
Duty Cycle Distortion .........................................................................................................................
DCD Measurement Techniques ...................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
5–18
5–23
5–29
5–30
5–31
5–33
Chapter 6. Reference & Ordering Information
Software ..................................................................................................................................................
Device Pin-Outs .....................................................................................................................................
Ordering Information ...........................................................................................................................
Document Revision History .................................................................................................................
Section II. Clock Management
Revision History .................................................................................................................................... 6–1
Chapter 7. PLLs in Cyclone II Devices
Introduction ............................................................................................................................................ 7–1
Cyclone II PLL Hardware Overview .................................................................................................. 7–2
PLL Reference Clock Generation ................................................................................................... 7–6
Clock Feedback Modes ....................................................................................................................... 7–10
Normal Mode .................................................................................................................................. 7–10
Zero Delay Buffer Mode ................................................................................................................ 7–11
No Compensation Mode ............................................................................................................... 7–12
Source-Synchronous Mode ........................................................................................................... 7–13
Hardware Features .............................................................................................................................. 7–14
Clock Multiplication & Division .................................................................................................. 7–14
Programmable Duty Cycle ........................................................................................................... 7–15
Phase-Shifting Implementation .................................................................................................... 7–16
Control Signals ................................................................................................................................ 7–17
Manual Clock Switchover ............................................................................................................. 7–20
Clocking ................................................................................................................................................ 7–21
Global Clock Network ................................................................................................................... 7–21
Clock Control Block ....................................................................................................................... 7–24
Global Clock Network Clock Source Generation ...................................................................... 7–26
Global Clock Network Power Down ........................................................................................... 7–28
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