Timing Specifications
Table 5–43. Cyclone II I/O Output Delay for Row Pins (Part 4 of 4)
Fast Corner
I/O Standard
Drive
Parameter Industrial
Strength
/Auto-
motive
—
t
O P
t
D I P
RSDS
—
t
O P
t
D I P
MINI_LVDS
—
t
O P
t
D I P
PCI
—
t
O P
t
D I P
PCI-X
—
t
O P
t
D I P
Notes to
Table 5–43:
(1)
(2)
(3)
This is the default setting in the Quartus II software.
These numbers are for commercial devices.
These numbers are for automotive devices.
Commer-
cial
1275
1407
1275
1407
1275
1407
1036
1168
1036
1168
–6
Speed
Grade
2089
2297
2089
2297
2089
2297
2070
2278
2070
2278
–7
Speed
Grade
(2)
2184
2421
2184
2421
2184
2421
2214
2451
2214
2451
–7
Speed
Grade
(3)
2272
2545
2272
2545
2272
2545
2352
2625
2352
2625
–8
Speed
Grade
2278
2545
2278
2545
2278
2545
2358
2625
2358
2625
Unit
LVDS
1216
1340
1216
1340
1216
1340
989
1113
989
1113
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Maximum Input and Output Clock Rate
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–44
specifies the maximum input clock toggle rates.
Table 5–45
specifies the maximum output clock toggle rates at default load.
Table 5–46
specifies the derating factors for the output clock toggle rate
for non-default load.
To calculate the output toggle rate for a non-default load, use this
formula:
The toggle rate for a non-default load
5–46
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
