Timing Specifications
IOE Programmable Delay
Refer to Table 5–36 and 5–37 for IOE programmable delay.
Table 5–36. Cyclone II IOE Programmable Delay on Column Pins Notes (1), (2)
–7 Speed
Grade
Fast Corner
–6 Speed
Grade
–8 Speed
Grade
Number
of
(3)
(4)
Parameter Paths Affected
Unit
Settings
Min Max Min Max Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
Input Delay Pad -> I/O
from Pin to dataout to core
Internal
7
8
2
0
0
2233
2344
0
3827
—
0
0
4232
4088
0
4349
—
ps
ps
—
—
Cells
Input Delay Pad -> I/O
from Pin to input register
Input
0
0
2656
2788
0
4555
—
0
0
4914
4748
0
4940
—
ps
ps
—
—
Register
Delay from I/O output
0
0
303
318
0
563
—
0
0
638
617
0
670
—
ps
ps
Output
register -> Pad
—
—
Register to
Output Pin
Notes to Table 5–36:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
(3) The value in the first row for each parameter represents the fast corner timing parameter for industrial and
automotive devices. The second row represents the fast corner timing parameter for commercial devices.
(4) The value in the first row is for automotive devices. The second row is for commercial devices.
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins Notes (1), (2) (Part 1 of 2)
–6 Speed
Grade
–7 Speed
Grade (4)
Fast Corner (3)
–8 Speed Grade
Number
of
Settings
Paths
Affected
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
InputDelay Pad ->
from Pin to I/O
7
0
0
2240
2352
0
3776
—
0
0
4174
4033
0
4290
—
ps
ps
—
—
Internal
Cells
dataout
to core
5–30
Altera Corporation
February 2008
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
