DC Characteristics and Timing Specifications
EP2C70 Clock Timing Parameters
Tables 5–33
and
5–34
show the clock timing parameters for EP2C70
devices.
Table 5–33. EP2C70 Column Pins Global Clock Timing Parameters
Fast Corner
Parameter
Industrial
t
C I N
t
C O U T
t
P L L C I N
t
P L L C O U T
1.575
1.589
–0.149
–0.135
Commercial
1.651
1.666
–0.158
–0.143
–6 Speed
Grade
2.914
2.948
0.27
0.304
–7 Speed
Grade
3.105
3.137
0.268
0.3
–8 Speed
Grade
3.174
3.203
0.089
0.118
Unit
ns
ns
ns
ns
Table 5–34. EP2C70 Row Pins Global Clock Timing Parameters
Fast Corner
Parameter
Industrial
t
C I N
t
C O U T
t
P L L C I N
t
P L L C O U T
1.463
1.465
–0.261
–0.259
Commercial
1.533
1.535
–0.276
–0.274
–6 Speed
Grade
2.753
2.769
0.109
0.125
–7 Speed
Grade
2.927
2.940
0.09
0.103
–8 Speed
Grade
3.010
3.018
–0.075
–0.067
Unit
ns
ns
ns
ns
Clock Network Skew Adders
Table 5–35
shows the clock network specifications.
Table 5–35. Clock Network Specifications
Name
Clock skew adder
EP2C5/A, EP2C8/A
(1)
Description
Inter-clock network, same bank
Inter-clock network, same side and
entire chip
Inter-clock network, same bank
Inter-clock network, same side and
entire chip
Max
±88
±88
±118
±138
Unit
ps
ps
ps
ps
Clock skew adder
EP2C15A, EP2C20/A,
EP2C35, EP2C50,
EP2C70
(1)
Note to
Table 5–35:
(1)
This is in addition to intra-clock network skew, which is modeled in the
Quartus II software.
Altera Corporation
February 2008
5–29
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
