DDR Memory Interface Pins
The DQS pins are listed in the Cyclone II pin tables as DQS[1..0]T,
DQS[1..0]B, DQS[1..0]L, and DQS[1..0]Rfor the EP2C5 and EP2C8
devices and DQS[5..0]T, DQS[5..0]B, DQS[3..0]L, and
DQS[3..0]Rfor the larger devices. The Tdenotes pins on the top of the
device, the Bdenotes pins on the bottom of the device, the Ldenotes pins
on the left of the device, and the Rdenotes pins on the right of the device.
The corresponding DQ pins are marked as DQ[5..0]T[8..0],
where [5..0]indicates which DQS group the pins belong to.
In the Cyclone II pinouts, the DQ groups with 9 DQ pins are also used in
the ×8 mode with the corresponding DQS pins, leaving the unused DQ
pin available as a regular I/O pin. The DQ groups that have 18 DQ pins
are also used in the ×16 mode with the corresponding DQS pins, leaving
the two unused DQ pins available as regular I/O pins. For example,
DQ1T[8..0]can be used in the ×8 mode, provided it is used with DQS1T.
The remaining unused DQ pin, DQ1T8, is available as a regular I/O pin.
When not used as DQ or DQS pins, these pins are available as regular I/O
pins. Table 9–3 shows the number of DQS pins supported in each I/O
bank in each Cyclone II device density.
Table 9–3. Available DQS Pins in Each I/O Bank & Each Device
Note (1)
Device
Top I/O Bank
DQS[1..0]T
DQS[5..0]B
Bottom I/O Bank
DQS[1..0]B
DQS[5..0]T
Left I/O Bank
DQS[1..0]L
DQS[3..0]L
Right I/O Bank
DQS[1..0]R
DQS[3..0]R
EP2C5, EP2C8
EP2C15, EP2C20,
EP2C35, EP2C50,
EP2C70
Note to Table 9–3:
(1) Numbers are preliminary.
The DQ pin numbering is based on ×8/×9 mode. There are up to 8
DQS/DQ groups in ×8 mode or 4 DQS/DQ groups in ×9 mode in I/O
banks for EP2C5 and EP2C8. For the larger devices, there are up to 20
DQS/DQ groups in ×8 mode or 8 DQS/DQ groups in ×9 mode. Although
there are up to 20 DQS/DQ groups in the ×8 mode available in the larger
Cyclone II devices, but because of the available clock resources in the
Cyclone II devices, only 16 DQS/DQ groups can be utilized for the
external memory interface. There is a total of 16 global clock buses
available for routing DQS signals but 2 of them are needed for routing the
–90° write clock and the system clock to the external memory devices.
This reduces the global clock resources to 14 global clock buses for
routing DQS signals. Incoming DQS signals are all routed to the clock
control block, and are then routed to the global clock bus to clock the DDR
LE registers. For EP2C5 and EP2C8 devices, the DQS signals are routed
9–12
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
