Cyclone II Memory Blocks
Figure 8–17. Cyclone II Read/Write Clock Mode
Notes (1), (2)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
Data In
512 ´ 8
data[ ]
D
ENA
Q
Q
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
rdaddress[ ]
Read Address
D
ENA
To MultiTrack
Interconnect (2)
Data Out
D
Q
ENA
byteena[ ]
Byte Enable
D
ENA
Q
Q
wraddress[ ]
Write Address
D
ENA
Read Address
Clock Enable
rd_addressstall
wr_addressstall
Write Address
Clock Enable
(1)
rden
Read Enable
Write Enable
D
Q
ENA
wren
rdclocken
Write
Pulse
Generator
D
ENA
Q
wrclocken
wrclock
rdclock
Notes to Figure 8–17:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) For more information about the MultiTract interconnect, refer to Cyclone II Device Family Data Sheet in volume 1 of
the Cyclone II Device Handbook.
Altera Corporation
February 2008
8–23
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
