Cyclone II Memory Blocks
Figure 8–15. Cyclone II Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2)
6 LAB Row
Clocks
Memory Block
256 ´ 16
6
data[ ]
D
ENA
Q
Q
Data In
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
rdaddress[ ]
Read Address
D
ENA
To MultiTrack
Interconnect (2)
Data Out
D
Q
ENA
byteena[ ]
Byte Enable
D
ENA
Q
Q
wraddress[ ]
Write Address
D
ENA
Read Address
Clock Enable
rd_addressstall
wr_addressstall
Write Address
Clock Enable
(1)
rden
Read Enable
Write Enable
D
Q
ENA
wren
outclocken
Write
Pulse
Generator
D
ENA
Q
inclocken
inclock
outclock
Notes to Figure 8–15:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) See the Cyclone II Device Family Data Sheet in volume 1 of the Cyclone II Device Handbook for more information on the
MultiTrack™ interconnect.
Altera Corporation
February 2008
8–21
Cyclone II Device Handbook, Volume 1