Cyclone II Memory Blocks
Figure 8–10. Cyclone II True Dual-Port Mode
Note (1)
data_a[]
data_b[]
address_b[]
wren_b
address_a[]
wren_a
byteena_a[]
addressstall_a
clock_a
byteena_b[]
addressstall_b
clock_b
enable_b
enable_a
aclr_a
q_a[ ]
aclr_b
q_b[]
Note to Figure 8–10:
(1) True dual-port memory supports input and output clock mode in addition to the
independent clock mode shown.
The widest bit configuration of the M4K blocks in true dual-port mode is
256 × 16-bit (18-bit with parity).
The 128 × 32-bit (36-bit with parity) configuration of the M4K block is
unavailable because the number of output drivers is equivalent to the
maximum bit width. The maximum width of the true dual-port RAM
equals half of the total number of output drivers because true dual-port
RAM has outputs on two ports. Table 8–6 lists the possible M4K block
mixed-port width configurations.
Table 8–6. Cyclone II Memory Block Mixed-Port Width Configurations (True
Dual-Port)
Write Port
Read Port
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 512 × 9 256 × 18
4K × 1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
v
v
v
v
In true dual-port configuration, the RAM outputs are in
read-during-write mode. This means that during a write operation, data
being written to the A or B port of the RAM flows through to the A or B
Altera Corporation
February 2008
8–13
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
