Memory Modes
address. See “Read-During- Write Operation at the Same Address” on
page 8–28 for more information. Figure 8–9 shows timing waveforms for
read and write operations in simple dual-port mode.
Figure 8–9. Cyclone II Simple Dual-Port Timing Waveforms
wrclock
wren
an
a0
a1
a2
a3
a4
a5
an-1
a6
wraddress
data (1)
din-1
din
din4
din5
din6
rdclock
rden
bn
b1
b2
b3
b0
rdaddress
q (synch)
doutn
doutn-1
dout0
doutn-2
doutn-1
q (asynch)
doutn
dout0
Note to Figure 8–9:
(1) The crosses in the datawaveform during read mean “don’t care.”
True Dual-Port Mode
True dual-port mode supports any combination of two-port operations:
two reads, two writes, or one read and one write at two different clock
frequencies. Figure 8–10 shows Cyclone II true dual-port memory
configuration.
8–12
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
